The present invention relates to a solid-state imaging apparatus for use in a camcorder, a digital still camera, and others and, more specifically, to a solid-state imaging apparatus using an amplified solid-state imaging device that has an amplifier capability in an imaging area.
Imaging apparatuses such as digital cameras have recently started using MOS (Metal Oxide Semiconductor) image sensors. The MOS image sensors each have an active element in a pixel as an imaging device, thereby allowing on-chip peripheral circuits. FIG. 1 shows the circuit configuration of a MOS image sensor of a general type. The general MOS image sensor usually carries a plurality of pixels arranged two dimensionally, but for simplification, FIG. 1 shows only three pixels P11, P12, and P13 arranged in a row. These pixels P11, P12, and P13 are configured to each include a photodiode PD, a transfer transistor M1, a reset transistor M2, and a selection transistor M4, and respectively include floating diffusion sections FD11, FD12, and FD13, and amplification transistors M311, M312, and M313. The floating diffusion sections FD11, FD12, and FD13 are those each having a capacitance. The pixels P11, P12, and P13 are coupled to each corresponding correlated double sampling circuit (CDS circuit) 10 respectively via vertical signal lines 31, 32, and 33. The vertical signal lines 31, 32, and 33 are respectively coupled to bias transistors M51, M52, and M53 at their each one end. The bias transistors M51, M52, and M53 each serve as a constant-current source with their other ends being-grounded. These bias transistors M51, M52, and M53 are under the control of a bias current adjusting voltage Vbias.
The CDS circuits 10 are each configured to include a clamp transistor M11, a sample hold transistor M12, a clamp capacitor C11, and a sample hold capacitor C12. The CDS circuits 10 are coupled to a horizontal signal line 7 via their corresponding column selection transistors M6, and are so configured as to output image signals via an output amplifier 5. Various types of pulses are provided respectively from a vertical scanning section 2 and a horizontal scanning section 4 under the control of a timing control section 6. The various types of pulses include a transfer pulse φTR1, a reset pulse φRST1, and a row selection pulse φROW1, which are respectively related to the control of the transistors in each of the pixels, i.e., the transfer transistor M1, the reset transistor M2, and the selection transistor M4. The various types of pulses also include column selection pulses φH1, φH2, and φH3, which are related to the control of the column selection transistors M6. Other pulses related to the control of the clamp transistor M11 and the sample hold transistor M12, i.e., a clamp pulse φCL, and a sample hold pulse φSH, are to be output from the timing control section 6.
The MOS image sensor configured as above suffers from image quality deterioration due to the varying threshold value of the amplification transistors M311 to M313, and the reset noise of the reset transistor M2 in every pixel. However, such noise can be removed by finding a pixel-output difference in each of the CDS circuits 10, i.e., a difference between the pixel output after the resetting and the pixel output after the transferring of the signal charges of the photodiode PD. With the noise favorably removed as such, only optical signals serving as image signals can be output.
The MOS image sensor provided with the CDS circuits is known to generate, when a high-luminance light enters thereinto, a completely black image that looks like a result of no entry of light. Such a phenomenon is hereinafter referred to as black sun phenomenon. Described next is such a black sun phenomenon in the MOS image sensor. FIG. 2 is a timing chart for illustrating the operation of causing the black sun phenomenon when a high-luminance object is imaged. Exemplified here is a case where a high-luminance light is being directed to the center pixel P12 of FIG. 1, but a light is hardly entered to the remaining pixels P11 and P13.
(1) First of all, in a reset period T1, when a row selection pulse φROW1 is in the state of H (High) level, a reset pulse φRST1 is set to the H level, and the floating diffusion sections FD11, FD12, and FD13 of each pixel are fixed to a power supply voltage VDD. In the CDS circuits 10, a clamp pulse φCL and a sample hold pulse φSH are both set to the H level.
(2) In the next reset sampling period T2, the reset pulse φRST1 is set to the L (Low) level. In this period, in the pixels P11 and P13 not being exposed to a high-luminance light, the floating diffusion sections FD11 and FD13 respectively show no change of their voltages VFD11 and VFD13 (VFD13 is not shown), but in the pixel P12 being exposed to a high-luminance light, the floating diffusion section FD12 drops its voltage VFD12 as shown in the drawing due to the leakage of charge from the photodiode PD, for example. This resultantly causes the reduction of a potential V32(Rst) of the vertical signal line 32 that is coupled with the pixel P12, thereby deriving (VFD12−VGS-M312). Note here that this term of VGS-M312 denotes the gate-source voltage of the amplifier transistor M312 of the pixel P12. At the end of the reset sampling period T2, the potential of each of the vertical signal lines 31 to 33 are clamped with the clamp pulse φCL being set to the L level in the CDS circuits 10.
(3) In the following signal transfer period T3, with a transfer pulse φTR1 being set to the H level, the signal charges of the photodiode PD in each of the pixels P11 to P13 are transferred to their corresponding floating diffusion sections FD11 to FD13. At this time, the voltage VFD12 of the floating diffusion section FD12 in the pixel P12 being exposed to the high-luminance light is already reduced in the reset sampling period T2. Therefore, even if the charges of the photodiode PD are transferred, the resulting voltage change is not that much from the value in the reset sampling period T2, i.e., no voltage change is observed when the voltage VFD12 of the floating diffusion section FD12 has reached its bottom value due to the leakage of charge. As a result, the vertical signal 32 also shows a slight change of the potential V32(Sig). Note here that, at this time, because the pixels P11 and P13 are assumed as being hardly exposed to a light, the remaining vertical signal lines 31 and 33 also hardly show a change of potential.
(4) In the following signal sampling period T4, with the processing operation of the CDS circuits 10, the potential difference [V32(Rst)−V32(Sig)] is retained at the sample hold capacitor C12. The potential difference being the processing result in each of the CDS circuits 10 are output as image signals via the column selection transistors M6 and the output amplifier 5. At this time, in the pixel P12 being exposed to the high-luminance light, a black sun phenomenon is observed due to the variation of the potential V32(Rst) of the vertical signal line 32 in the reset sampling period T2, i.e., the potential difference [V32(Rst)−V32(Sig)] being the CDS processing result is small, and thus the output looking black is output as an image signal.
Such a problem of black sun phenomenon can be solved with still image shooting if a mechanical shutter is provided. However, with moving image shooting not using a mechanical shutter, for example, the black sun phenomenon is inevitable.
There is another concern that the entering of the high-luminance light may affect any pixel areas other than the pixel being exposed thereto. FIG. 3 is a timing chart for illustrating the operation of causing a highlight transverse stripe phenomenon to be observed around the pixel being exposed to a high-luminance light. Exemplified here is also a case where a high-luminance light is being directed to the center pixel P12 of FIG. 1, but a light is hardly entered to the remaining pixels P11 and P13. This example is with an assumption that no black sun phenomenon is to be observed.
(1) First of all, in the reset period T1, similarly, when a row selection pulse φROW1 is in the state of H level, a reset pulse φRST1 is set to the H level, and the voltages of the floating diffusion sections FD11, FD12, and FD13 of each of the pixels, i.e., voltages VFD11 to VFD13, are all fixed to the power supply voltage VDD. In the CDS circuits 10, a clamp pulse φCL and a sample hold pulse φSH are both set to the H level.
(2) In the next reset sampling period T2, at the end thereof, the clamp pulse φCL is set to the L level in the CDS circuits 10, and the voltages of the floating diffusion sections FD11 to FD13 of each of the pixels are clamped to the CDS circuits 10 respectively via the vertical signal lines 31 to 33.
(3) In the following signal transfer period T3, with a transfer pulse φTR1 being set to the H level, the signal charges of the photodiode PD in each of the pixels P11 to P13 are transferred to their corresponding floating diffusion sections FD11 to FD13. At this time, the voltage VFD12 of the floating diffusion section FD12 in the pixel P12 being exposed to the high-luminance light is largely reduced from the power supply voltage VDD due to the large amount of signal charges therein. Therefore, the potential V32 of the vertical signal line 32 coupled with the pixel P12 is largely reduced down to (VFD12−VGS-M312). This accordingly reduces the drain-source voltage of the bias transistor M52 coupled to the vertical signal line 32, thereby reducing the current flowing to the bias transistor M52. This reduction of the current thus reduces any possible voltage drop to be caused by the GND resistance of a GND line coupled to all of the sources of the bias transistors M51 to M53 so that the gate-source voltage is increased in the bias transistors M51 and M53 respectively coupled to the vertical signal lines 31 and 33. As a result, the current flowing to the vertical signal lines 31 and 33 is increased. This increase of the current then increases the gate-source voltage in the amplification transistors M311 and M313 of the pixels P11 and P13, respectively, so that the potentials V31 and V33 of the vertical signal lines 31 and 33 will be in the level lower by ΔV than the reset level output (VDD).
(4) In the following signal sampling period T4, with the processing operation of the CDS circuits 10, the difference between the reset potential and the optical-signal-reading potential after the transferring of the signal charges in the vertical signal lines 31 to 33 is output as an image signal via the column selection transistors M6 and the output amplifier 5. At this time, in the pixels P11 and P13 in the vicinity of the pixel P12 being exposed to the high-luminance light, the potential difference ΔV from the reset level is detected due to the variation of the current via the GND line coupled to the bias transistor M52 as described above. Thus detected potential difference ΔV will look a white float-like image, thereby causing the highlight transverse stripe phenomenon in the image signal.
In the MOS image sensor as such, when a window chart is imaged, such images as shown in FIGS. 4A to 4D may be derived due to the black sun phenomenon and the highlight transverse stripe phenomenon. FIG. 4A shows the pattern of an object with a high-luminance light at the center, and FIG. 4B shows the state in which the black sun phenomenon is observed due to the variation of the reset potential. FIG. 4C shows the state in which the highlight transverse stripe phenomenon is observed due to the variation of the signal potential, and FIG. 4D shows the state in which the black sun phenomenon is observed together with the highlight transverse stripe phenomenon.
JP-A-2007-20156 describes the previous technique as below not to cause the black sun phenomenon and the highlight transverse stripe phenomenon in the MOS image sensor described above. That is, with the technique, as shown in FIG. 5, clipping circuits 71 to 73 are provided respectively to the vertical signal lines 31 to 33 to selectively restrict the potentials thereof to be the value of a first or second potential. With such a configuration, the pixel output after the resetting of the pixels is so controlled as not to be the value of the first potential or lower, and the pixel output after the transferring of the signal charges is so controlled as not to be the value of the second potential or lower. Note here that the clipping circuits 71 to 73 are respectively configured to include clipping transistors M71 to M73, and clipping selection transistors M81 to M83. In the configuration, the gates of the clipping transistors M71 to M73 are coupled to a clipping voltage Vclip, and the drains thereof are coupled to the power supply voltage VDD. The gates of the clipping selection transistors M81 to M83 are applied with a clipping selection pulse φROWD, and the sources thereof are respectively coupled to the vertical signal lines 31 to 33. The clipping voltage Vclip and the clipping selection pulse φROWD are to be output from the timing control circuit 6.
Described next is the operation of the MOS image sensor provided with the clipping circuits as in the above configuration by referring to the timing chart of FIG. 6. Exemplified also here is a case where a high-luminance light is being directed to the center pixel P12 of FIG. 5, but a light is hardly entered to the remaining pixels P11 and P13 therearound.
(1) First of all, in the reset period T1, a row selection pulse φROW1 is set to the H level, and the clipping voltage Vclip is set to a first level VclipH, i.e., the level being lower than the power supply voltage VDD but not causing the black sun phenomenon. A reset pulse φRST1 is set to the H level, and the floating diffusion sections FD11, FD12, and FD13 of each of the pixels are fixed to the power supply voltage VDD. In the CDS circuits 10, a clamp pulse φCL and a sample hold pulse φSH are both set to the H level.
(2) In the next reset sampling period T2, in the pixel P12 being exposed to a high-luminance light, the floating diffusion section FD12 shows a considerable reduction of its voltage VFD12 due to the leakage of charge from the photodiode PD, for example. As a result, when there is no clipping circuit provided, the potential V32 of the vertical signal line 32 is also reduced to a considerable degree. In this example, however, with the clipping circuit 72 provided, the potential V32(Rst) of the vertical signal line 32 will not be reduced to or below the potential of (VclipH−VGS-M72) as is clipped thereto. This accordingly prevents any possible black sun phenomenon from occurring also by the differential processing to be executed next by the CDS circuits 10. Note here that the term of VGS-M72 denotes the gate-source voltage of the clipping transistor M72. At the end of the reset sampling period T2, the potentials of the vertical signal lines 31 to 33 are clamped with the clamp pulse φCL being in the L level in the CDS circuits 10.
(3) In the following signal transfer period T3, the level of the clipping voltage Vclip is changed to a second level VclipL in which no highlight transverse stripe phenomenon is to be caused, and by setting the transfer pulse φTR1 to the H level, the charges of the photodiode PD in each of the pixels P11 to P13 are transferred to the corresponding floating diffusion sections FD11 to FD13. At this time, the voltage VFD12 of the floating diffusion section FD12 in the pixel P12 being exposed to the high-luminance light is largely reduced. As such, when there is no clipping circuit provided, the potential V32 of the vertical signal line 32 is also largely reduced, and the drain-source voltage of the bias transistor M51 is reduced down to a value outside of the range of operating the bias transistor M51, thereby causing highlight transverse stripe. However, if the voltage of the clipping circuit, i.e., voltage VDD2, is set to the second clipping level VclipL, the voltage V32 of the vertical signal line 32 will not down to or below the value of (VclipL−VGS-M72) as is clipped thereto, thereby operating the bias transistor M51. This accordingly prevents any possible highlight transverse stripe from occurring.
(4) In the following signal sampling period T4, with the processing operation of the CDS circuits 10, the potential difference of the vertical signal lines 31 to 33, i.e., the difference between the reset potential and the optical-signal-reading potential after the transferring of the signal charges, is retained at the sample hold capacity C12. The potential difference is then output, via the column selection transistors M6 and the output amplifier 5, as an image signal free from the black sun phenomenon and the highlight transverse stripe phenomenon.
As described above, with the clipping circuits provided as such, any possible black sun phenomenon and highlight transverse stripe phenomenon can be both favorably prevented.